/* $Id$ */
/* vim: set filetype=verilog ts=8 sw=4 tw=132: */
/*****************************************************************************
 
              (c) Copyright 1987 - 2012,  VIA Technologies, Inc.       
                            ALL RIGHTS RESERVED                            
                                                                     
 This design and all of its related documentation constitutes valuable and
 confidential property of VIA Technologies, Inc.  No part of it may be
 reproduced in any form or by any means   used to make any transformation
 / adaptation / redistribution without the prior written permission from the
 copyright holders. 
 
------------------------------------------------------------------------------

  DESCRIPTION:

  FEATURES:

  TODO:

  AUTHORS:
     Shawn Fang
    
------------------------------------------------------------------------------
                             REVISION HISTORY
    $Log$

*****************************************************************************/
module ppregs_D
    (
	input  clock,
	input  reset,
	input  D_stall,
        input  D_bubble,
	input  [3:0]icode_i,
	input  [3:0]ifun_i,
	input  [3:0]rA_i,
	input  [3:0]rB_i,
	input  [31:0]valC_i,
	input  [31:0]valP_i,
	
	output reg [3:0]icode_o,
	output reg [3:0]ifun_o,
	output reg [3:0]rA_o,
	output reg [3:0]rB_o,
	output reg [31:0]valC_o,
	output reg [31:0]valP_o
    );

    always @ (posedge clock or posedge reset)
    begin
	if(reset)
	    begin
		icode_o<=`IBUB;
		ifun_o<=4'h0;
		rA_o<=`RNUL;
		rB_o<=`RNUL;
		valC_o<=32'h0;
		valP_o<=32'h0;
	    end
	else
	    begin
		if(D_stall)
		begin
		   icode_o<=icode_o;
		    ifun_o<=ifun_o;
		    rA_o<=rA_o;
		    rB_o<=rB_o;
		    valC_o<=valC_o;
		    valP_o<=valP_o;
		end
		else if(D_bubble)
		begin
		    icode_o<=`IBUB;
		    ifun_o<=4'h0;
		    rA_o<=`RNUL;
		    rB_o<=`RNUL;
		    valC_o<=32'h0;
		    valP_o<=32'h0;
		end
		else
		begin
		    icode_o<=icode_i;
		    ifun_o<=ifun_i;
		    rA_o<=rA_i;
		    rB_o<=rB_i;
		    valC_o<=valC_i;
		    valP_o<=valP_i;
		end

	    end
    end


endmodule
